Redmine project: ​http://gauss.bu.edu/redmine/projects/hyper-k-tdc

Reference

• ​NIM Article on the QTC chip
• ​KLOE-2 TDC paper -- interesting four-phase low resource FPGA with 625ps resolution in Virtex-5
• QBEE board ​photo

Design Thoughts

• ​TKO spec (page 4) says max component height is 0.39" (9.9mm). ​FMC spec (page 23) says minimum stacking height is 8.5mm. This does not accommodate a 1.6mm standard thickness PCB.
• Samtec ​LSEM series and similar connectors with stack heights down to 6mm exist.