This page will document development work on an efficient Aurora 66b/64b protocol decoder block for use the the CMS IT-DTC and potentially other applications.
In the IT-DTC, Aurora-encoded data will be received at 32 bit words every 25ns (40MHz word rate), for an equivalent bit rate of 1.28 Gbps. The challenge is to develop an efficient decoder which can acquire synchronization to the 66 bit frames and deliver decoded (descrambled) data to the output.
Note that in a typical Aurora application (as described in the Xilinx documentation, e.g.) the data is received directly by a deserializer and processed one bit at a time. In our case instead we receive the data as 32-bit words from the lpGBT-FPGA decoder core.
August 2019
A receiver and descrambler was created to handle the Aurora-encoded data. The design of the rx module mirrors the overall structure laid out in the MSU Thesis refrence.
SVN: http://gauss.bu.edu/svn/cms-tracker/TestFirmware/Aurora
The following tables show the resource utilization for a single module of the rx_body
-Michael Kremer
Reference
- LPGBT: ACES 2016 talk ACES 2018 talk Tutorial
- GBT-FPGA Project page Documentation
- Aurora protocol specification (Xilinx) * 10 GbE page 262+
- MSU Thesis: http://cds.cern.ch/record/2631488/files/CERN-THESIS-2018-100.pdf?subformat=pdfa&version=1
- scrambler/descrambler block diagram
