C Program Test Software


External SRAM

Internal Memory

Initial Test

Hardware Testing

Preliminary Results

Setup Info

The plots below were created using an ADC with a sampling rate of 40 MHz and a .5 microsecond, square, positive-going pulse-wave.

The first image represents the pulse sent out from the op-amp (the blue pattern) and the corresponding analog signal sent into the ADC (the gray pattern). For the first 5 microseconds from the time the pulse is first sent out, the ADC is saturated. Then, after around 12 microseconds (which corresponds to 500 samples captured by the ADC), the first echo occurs--the very thin spike on the gray trace. After another 14 microseconds, a longer, secondary echo occurs.

The ADCs interpretation of these events can be seen in the second image. Samples from the ADC are not being sent into the memory during the first 5 microseconds of chaos so that interval is excluded from the picture. However, the first and second echoes are present in much the same form and location as would be expected from looking at the oscilloscope patterns shown in the other image. A third echo is present in the plots from the ADC that would have been located somewhere far off to the right in the first image. The three different graphs are simply different magnifications of the same data.

The op-amp and amplification circuitry currently distort the pulse into a triangle-shaped peak around 1 microsecond wide. Also, when not active, the op-amp settles at a small (approximately 20 millivolt), but non-zero, voltage. This voltage accounts for the small, but perceptible, capacitor-charging curve overlaid with the pulses in the graphs of the second image. We are attempting to fix both these problems.



Note that, in these graphs, full range in the y-axis = 4000 counts = 75 millivolts and full range in the x-axis = 16000 samples = 400 microseconds.

Design Discussion

Current plan is to use a XC3S500E (datasheet) in a PQ208 package, with an external synchronous SRAM.

For example, a Cypress CY7C1352G-133AXC (datasheet)

This is a 256k x 18 133MHz synchronous static RAM (SRAM). It requires a clock, which can be up to 133MHz (80MHz and 120MHz would be reasonable choices in our design).

If we ran it at 80MHz, we would get 18x2 or 36 bits per clock, so we could record three channels of Rx data. In Tx mode there is only one channel, so there wouldnt be a problem with 14 bits.

Reference Information and Design Resources

  • "Novel Transmit Protection Scheme for Ultrasound Systems" – Article Link
  • "A new SPICE Model of Power P-I-N Diode Based on Asymptotic Waveform Evaluation" – Article Link

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Last modified 10 years ago Last modified on Nov 8, 2013, 10:17:53 AM