This page documents a proposed 12-bit WFD for PMT pulse digitization. The goal is initially to engineer an ADC/FPGA/memory block which is relatively straightforward and which could be replicated to produce a multi-channel unit with a (unspecified as of now) computer interface.

Some guideline specs for a production unit:

  • 12 or more bits resolution
  • 250MSPS or faster digitization
  • Front-end with 250MHz bandwidth to support interleaving of two FADCs at 500MSPS (or 500MSPS ADC). 12 bit analog performance, capable of 0.1mV least count operation.
  • generic memory interface (SDRAM) capable of 2x ADC speed (500MB/sec) throughput.
  • 50 ohm single-ended DC-coupled analog input, with adjustable gain and DC offset.
  • Baseline adjust such that both negative-going and positive-going signals can be accommodated
  • Convenient mechanism to combine multiple channels to extend dynamic range in pulse height or time (interleaving).

I would suggest an initial prototype with the following characteristics:

  • 50 ohm input, providing 0-4.095V (1mV/count) and 0-409.5mV (0.1mV/count) ranges.
  • On-board digitizer clock source, with external (sine wave) clock option
  • Suitable FADC and FPGA (Xilinx)
  • SDRAM with sufficient bandwidth
  • Ethernet (or USB-2) interface

'1GSPS and Beyond

'Candidate ADCs

'Other Parts

  • THS4509 wideband differential op-amp have_samples? Recommended to drive ADS5444. As of 4/5/07: THS4509RGTT 163pcs stock at Digikey 8.30

in small qtys, 5.60250 100pcs other distributers have stock as well

Existing Products

Last modified 9 years ago Last modified on Nov 8, 2013, 10:17:54 AM