Investigating J1 Forth CPU

2011-10-06, hazen

Downloaded verilog and put it in a Xilinx project for Spartan-6. Got it to compile, after figuring out that the S6 BRAMs require the SSRA and SSRB pins to be connected.

Last modified 9 years ago Last modified on Nov 8, 2013, 10:17:54 AM