Changes between Initial Version and Version 1 of DosiFirmware

Nov 8, 2013, 10:17:53 AM (9 years ago)
Eric Hazen



  • DosiFirmware

    v1 v1  
     1Back to [[Roblyer_dDOSI]]
     3The DOSI system consists of:
     5* One [ ADC12D1800RFRB]
     6* Up to six [ AD9910/eb]
     7* One [ Custom FPGA board]
     9This page describes the firmware requirements for the custom FPGA board.  Referring to the first page of the FPGA board document, ADC data is received from the FPGA board continuously (once it is initialized) on four groups of 12 LVDS pairs, each at 450MHz DDR (900Mb/s).  There are a few LVDS control signals which may or may not be important (see ADC12D1800RFRB documentation above).  These signals are received by the main FPGA (U2) on the PCB.  Also connected to this FPGA is an SFP fiber transceiver which provides a Gigabit Ethernet (GbE) interface.
     11A second FPGA (U1) provides control signals for all the DDS boards.  Four I/Os are routed between the two FPGAs to be used as a simple serial communications interface.  Both FPGAs are the same type, Xilinx Spartan-6LXT P/N XC6SLX45T-FGG484.
     13The firmware may be developed in two phases.
     15== Phase 1 Firmware ==
     17''''General requirements'''
     19* Provide GbE computer interface for control and readout (suggest use of IPBus).
     20* Receive DDR data from ADC and buffer in BRAM
     22* Provide efficient GbE readout of buffered data
     23* Provide a serial interface to access registers on the DDS boards
     24* Provide a parallel interface to control other I/Os on DDS (PROFILE[[2:0]]
     26The functions are partitioned as follows between the two FPGAs:
     28''''U2 (Main FPGA)'''
     30* GbE interface
     31* DDR data receiver and buffers
     32* Master for simple serial interface to U1
     34''''U1 (Slave FPGA)'''
     36* Slave for simple serial interface from U1
     37* For each of (6) DDS boards:
     38 * Serial interface to AD9910
     39 * Parallel interface for frequency setting
     40 * Control/readback of misc. control signals
     44* 4k samples on two channels.  Received as 4X 12-bit streams (two streams per ADC channel) so 1K DDR clocks per WF.
     45* 4k x 12 WF requires (4) 2k x 9 BRAMs, so 8 BRAMS needed per 2-channel capture cycle. 
     46* LX45T FPGA has 116 BRAMS.  Could store i.e. 12X capture cycles (96 BRAMs) and use remainder for IPBus buffering.
     48''''Register Layout'''
     50Present one capture cycle as 4k 32-bit words with two channels side-by-side in word
     51Operate as FIFO like DCC/AMC13 partitioned memory with "page advance" register to go to next waveform.
     56===  Current Version  ===
     58* [ DOSI firmware]