This page describes an effort to collaborate with Dinesh Loomba from the University of New Mexico on a negative ion drift TPC to search for the "Migdal effect".

== !Links/Doco

* Git:  https://gitlab.com/BU-EDF/edf-projects/dinesh-midgal (NOTE:  use "master" git branch)
* [[MigdalPcbFabNotes]] - Notes on PCB fabrication attempt starting January 2023
* SBND FPGA mezzanine: FPGA P/N: EP4CGX50DF27C7N

== Requirements

* Digitize 500 strips in X and Y (total 1000 strips) from the TPC and 1-2 MSPS
* Zero-suppress waveforms with pre- and post-samples, ideally supporting up to 100us per waveform
* Match waveforms with external trigger at ~100Hz (either firmware or software)
* Buffer and readout via Ethernet

== Current plan/proposal

* Obtain or fabricate (8) plus spares SBND or ProtoDUNE FEMB (front-end motherboard).  Each provides 128 channels of low-noise amplifier/shaper plus a commercial SPI ADC with max 3 MSPS.
* Obtain or design/fabricate an FPGA board which mounts on the FEMB
 * If we don't use the SBND one we could use Trenz TE0714 modules with XC7A50T-2CSG325I FPGA surplus from EMPHATIC
* Write firmware to readout the FPGA board using e.g. Ethernet
* Design and construct a simple trigger fanout system (could be integrated into a new FPGA board)
* Write software and debug/test/commission everything

== Major concerns

* Lack of available engineering
* Lack of Memory on FPGA modules
* Parts availability to build anything

== Some detailed thoughts

* XC7A50T FPGA (as on Trenz) has total 150 18k (36x512) BRAM blocks.
* ADC is AD7274BUJ (12 bits, up to 3MSPS sample rate)

One 18k BRAM could hold 512*3 12-bit samples with zero overhead.  At 2MSPS this is 768us.  So with ZS at least a handful of up to 100us waveform snippets.  One Trenz module has up to 138 I/Os.  So likely two would be needed to read out 128 channels.  This means that the RAM is probably OK.

FPGA board I/Os:

* 128 inputs from ADCs
* (8) each CS, CK, SDI, SDO to/from ASICs
* (4) each ADC SCK, CS output

Plus a few other random things (FE_xx_C, RST_FE)